The present invention relates to a level converter circuit, more particularly to a level converter circuit which converts the signal level being output from an integrated circuit (IC) memory device and the like into another arbitrary signal level.
Recently, it is often necessary to couple the output signals of transistor-transistor logic (TTL) or metal oxide semiconductor (MOS) IC's with the inputs of emitter coupled logic (ECL) IC's or to couple the output signals of ECL IC's with the input of TTL or MOS IC's. For example, the output signals of a random access memory (RAM) comprising MOS IC's may be coupled with the inputs of a logic circuit comprising ECL IC's. In such a case, it is necessary to convert the TTL signal level into an ECL signal level. Generally, for the TTL level, ground potential V.sub.SS is used as the base potential, for example, 0 V, and a voltage V.sub.CC, higher than ground potential V.sub.SS by, for example, 5 V, is used as the voltage supply. For the ECL level, ground potential V.sub.SS is used as the base potential, for example, 0 V, and a voltage V.sub.EE, lower than ground potential V.sub.SS by, for example, -5.2 V, is used as the voltage supply.
A prior art level converter circuit used for converting a TTL level into an ECL level is illustrated in FIG. 1. The level converter circuit of FIG. 1 comprises buffer circuit B.sub.1, PNP transistor Q.sub.1, and resistors R.sub.1, R.sub.2, and R.sub.3. The operation of the level converter circuit of FIG. 1 is illustrated in FIG. 2. The input signal supplied to the input terminal I.P. of the level converter circuit of FIG. 1 is a TTL level signal in the range between 0 V (V.sub.SS) and +5.0 V (V.sub.CC), as shown in FIG. 2. In the TTL level signal, the maximum level of the low "L" level signal is +0.4 V and the minimum level of the high "H" level signal is +2.4 V. The output signal of the level converter circuit of FIG. 1 is an ECL level signal in the range between 0 V (V.sub.SS) and -5.2 V (V.sub.EE). In the ECL level signal, the maximum level of the "L" level signal is -1.6 V, and the minimum level of the "H" level signal is -0.8 V.
The "H" level signal V.sub.H1 of the TTL level supplied to the input terminal I.P. is converted into the "H" level signal V.sub.H2 of the ECL level by the level converter circuit. The converted signal is output from output terminal O.P. Similarly, the "L" level signal V.sub.L1 of the TTL level supplied to the input terminal I.P. is converted into "L" level signal V.sub.L2 of the ECL level by the level converter circuit. The converted signal is output from output terminal O.P.
As described above, in the level converter circuit of FIG. 1, three voltage supply lines +5.0 V, 0 V, and -5.2 V are necessary. However, using three voltage supply lines is disadvantageous for increasing the integration scale of the IC.